1. Field of the Invention
The present invention is generally directed to improving the performance and energy consumption of processors.
2. Background Art
The evolution of modern processor architectures, in conjunction with technology scaling, has produced processors with high performance to meet increasing computational demands, and has also made power efficiency a paramount design objective for a wide array of enterprise-class and embedded processors. In addition to saving energy, reduction of power consumption can lead to dramatic benefits in reducing thermal hot spots and the cost of cooling for processors. To this end, dynamic voltage and frequency scaling (DVFS) has become a key avenue for achieving power efficiency via adjustment of the operating voltage and frequency of processors at runtime. DVFS schemes dynamically change a voltage and/or a frequency of a processor in response to one or more factors affecting a processor.
A central challenge in developing DVFS schemes is to balance two competing objectives: maximizing of power saving and ensuring tight fine-grain performance. The latter is particularly critical for latency-sensitive applications that require a high-degree of Quality of Service (QoS) or high levels of real-time responsiveness.
Conventional DVFS controllers are designed for specific application/workload. However, in many environments, general processor systems are required to switch between multiple applications/workloads with different characteristics. When a processor is subjected to multiple applications/workloads with different characteristics that go beyond the workloads originally envisioned, conventional DVFS systems may not yield adequate QoS or real-time responsiveness.